1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to high-performance integrated circuit capacitor structures.
2. Description of the Related Art
When integrated circuits are formed on a semiconductor substrate or chip, individual integrated circuit components or circuits can be subjected to current and voltage noise caused by other circuit elements on the chip or by external power supplies. To protect an electrical network or circuit area against noise from another circuit area or an external power supply, decoupling capacitors are formed on the chip to shunt the noise through the capacitor, thereby reducing the effect of the noise on the protected area. However, leading edge fabrication processes are not able to form planar decoupling capacitors with adequate decoupling capacitance to meet the noise protection requirements without consuming large amounts of valuable circuit area.
Accordingly, a need exists for an integrated circuit manufacturing process for fabricating decoupling capacitor structures which overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.